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Chapter 5: Using HIL
5–5
HIL Design Example
4. Replace the internal functions of the frequency sweep model with an HIL block.
Open the model FreqSweep_HIL.mdl from the FreqSweep directory (step 1 ).
Figure 5–4 shows this model, with the HIL block in place.
Figure 5–4. Frequency Sweep Design Model Using the HIL Block
5. Double-click the frequency sweep HIL block to display the Hardware in the loop
dialog box.
6. Select the Quartus II project by browsing into the FreqSweep_dspbuilder
directory to locate the FreqSweep.qpf file.
1
The full path to this file is visible in the dialog box when you select this file.
7. Select Clock from the list of available clock pins.
1
HIL does not support multiple clock domains and only the specified signal
is the HIL clock signal. The HIL treats any other clocks in your design as
input signals.
8. Select aclr from the list of available reset pins.
9. Identify the signed ports:
■
■
Select the Input port and click Unsigned .
Select each output port ( OutputCordic and OutputFilter ) and click Signed .
10. Select the reset level to be Active_High .
11. Select the mode of operation by turning off Burst Mode .
12. Click Next page . to display the second page of the Hardware in the loop dialog
box.
13. Specify a value for the FPGA device and click Compile with Quartus II to
compile the HIL design.
1
If no output writes to the MATLAB command window, check that the
original Quartus II project is up-to-date and compiles with he same version
of the Quartus II software that compiles your Simulink model.
14. Click Scan Jtag to find available cables and hardware devices in the chain.
15. Select the JTAG download cable that references the required FPGA device and
click Configure FPGA to program the FPGA on the board.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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